module async_fifo_tb;
    localparam DSIZE = 8;
    localparam ASIZE = 3;
    localparam MEMSIZE = 4;

    reg [DSIZE-1:0] wdata;
    wire [DSIZE-1:0] rdata;
    wire rempty;
    wire wfull;
    reg wval;
    reg ren;
    reg rclk;
    reg wclk;
    reg wreset;
    reg rreset;

    async_fifo #(.DSIZE(DSIZE),
        .ASIZE(ASIZE),
        .MEMSIZE(MEMSIZE)
    ) u_af(
        .rdata(rdata),
        .rempty(rempty),
        .wfull(wfull),
        .wdata(wdata),
        .wval(wval),
        .ren(ren),
        .rclk(rclk),
        .wclk(wclk),
        .wreset(wreset),
        .rreset(rreset)
    );

    initial begin
        rclk=1;
        forever #5 rclk=~rclk;
    end
    initial begin
        wclk=1;
        forever #7 wclk=~wclk;
    end
    initial begin
        wreset=1;
        rreset=1;
        @(posedge wclk);
        @(posedge rclk);
        @(posedge wclk);
        @(negedge wclk);
            wreset=0;
            rreset=0;
    end
    always @(negedge wclk) begin
        wval=$random;
        wdata=$random;
    end
    always @(negedge rclk) begin
        ren=$random;
    end
    initial begin
        repeat(100) @(posedge wclk);
        $finish;
    end
    // dump data
    initial begin
        $dumpfile("async_fifo_tb.vcd");
        $dumpvars;
    end
    always @(posedge wclk) begin
        if(~wreset && wval && ~wfull)
            $display("%t:w: %h",$time,wdata);
    end
    always @(posedge rclk) begin
        if(~rreset && ren && ~rempty)
            $display("%t:r: %h",$time,rdata); 
    end
endmodule

